In order to reduce the costs of future developments of modem communication systems, it is necessary to adapt existing circuits to new silicon processes and higher clock rates with as little effort as possible. With ever increasing clock speeds, it is necessary to build ever higher frequency clock generation circuits for handling clock distribution and synchronization. One example of an application of such circuits is in transmitters and receivers in gigabit Ethernet systems. As digital logic can be adapted more easily to new processes and higher clock rates than analog circuits, there is a general tendency to use digital circuits. Also, analog circuits drift, e.g., as a function of aging and temperature. All digital phase locked loops (ADPLL) are generally suggested to overcome these problems. Yet, known digital PLLs fail to provide a sufficiently quick response (locking) and long term stability.